S. M. Abbas, Y. Fan, J. Chen and C. Y. Tsui, “High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, pp. 1098-1111, March 2017.
Z. Qian, S. M. Abbas and C. Y. Tsui, "FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1854-1867, Sept. 2015.
S. M. Abbas, S. Lee, S. Baeg, S. Park, "An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory" IEEE Transactions on Computers, vol.PP, no.99, pp.1,1, doi: 10.1109/TC.2013.90
S. M. Abbas, Y. Fan, C. Y. Tsui, “Energy-Efficient Belief Propagation Decoder for Concatenated LDPC-Polar Code” to be submitted in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
S. M. Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine and Warren J. Gross "High-Throughput VLSI Architecture for soft decision decoding with ORBGRAND", in press, 2021 IEEE International Conference on Acoustics, Speech and Signal Processing.
S. M. Abbas, Thibaud Tonnellier, Furkan Ercan, Warren J. Gross "High-Throughput VLSI Architecture for GRAND," 2020 IEEE Workshop on Signal Processing Systems (SiPS), Coimbra, Portugal, 2020, pp. 1-6, doi: 10.1109/SiPS50750.2020.9195254.
S. M. Abbas, Y. Fan, J. Chen and C. Y. Tsui, “Concatenated LDPC-Polar Codes Decoding Through Belief Propagation” 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4.
S. M. Abbas and Chi-Ying Tsui, "Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO" 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Tallinn, 2016, pp. 1-5.
S. M. Abbas, YouZhe Fan, Ji Chen and Chi-Ying Tsui, "Low complexity belief propagation polar code decoder" IEEE Workshop on Signal Processing Systems (SiPS), 2015, Hangzhou, pp. 1-6.
S. M. Abbas, S. Hassan and Jongwon Yun, "Augmented reality based teaching pendant for industrial robot" International Conference on Control, Automation and Systems (ICCAS), 2012, pp. 2210-2213.
S. M. Abbas, Sanghyeon Baeg, Sungju Park “Multiple Cell Upsets tolerant Content Addressable Memory” International Reliability Physics Symposium (IRPS) April 2011, CA USA.
S. M. Abbas and Chi-Ying Tsui, “Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO” VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability.
Hardware architecture for Guessing Random Additive Noise Decoding (GRAND), S. M. Abbas, Thibaud Tonnellier, Warren J. Gross, Patent Applied, May 2020
Parallel LDPC decoder, H Lam, S. M. Abbas, Z Yang, Z Zhang, M Kwan, C Leung, K Tsang, US Patent App. 16/264,161, Dated: 08/06/2020
Method and apparatus for tolerating multi-cell upsets on content addressable memory, S. M. Abbas, S. Baeg, Patent Granted, Registration No. 1020100120903, Dated: 12th December, 2012.